Conventional approaches for implementing a digitally switched capacitor use transistor or diode switches in series with fixed value capacitors. A logic circuit is used to control which capacitors are connected through the switches to create a capacitance according to the particular needs of a user. Such an approach has several drawbacks. The maximum possible Q (quality factor) is limited by the resistance of the switching circuit. Since the resistance component of the capacitor is small, and the fixed capacitor values are small, resistance added by the switching circuit negatively impacts the Q factor of the entire circuit. A high Q factor capacitance is necessary for effectively implementing the circuit designs using the capacitor. Competitive products on the market tend to draw customer complaints when the Q factor is low (i.e., below 100).
Referring to FIG. 1, a circuit 10 is shown implementing a conventional approach for implementing a switched capacitor. The circuit 10 uses a number of switch devices 12a-12n in series with a number of fixed value capacitors 14a-14n. By changing the state (i.e., ON or OFF) of the switch devices 12a-12n, the respective fixed value capacitors 14a-14n are added or subtracted from the overall capacitance generated by the circuit 10. By closing the particular switch devices 12a-12n, the overall capacitance available to the application is varied. The fixed capacitors 14a-14n are typically set up in a configuration that enables a consistent step size of the capacitors 12a-12n. The circuit 10 can be used in applications such as digitally varied filter networks, oscillators, antenna matching circuits, amplifier feedback circuits, adaptive matching circuits, software-defined-radios, phase shifters, radar components, military electronic warfare applications, and other circuits where a variable capacitance would be useful. When using the circuit 10 as a capacitor in a circuit design, the resistive portion of the impedance becomes a problem and limits the “sharpness” of a resonance created by the circuit 10. The inaccuracy of the circuit 10 reduces the effectiveness of the abovementioned applications.
In particular, the switch devices 12a-12n are a limiting factor of the quality factor of the capacitance generated by the circuit 10. For a given semiconductor process, there are finite limits to how much the resistance of the switch devices 12a-12n can be lowered when turned on. As the overall size of the switch devices 12a-12n increases, the resistance when turned on decreases. However, other performance metrics (i.e., when the isolation decreases significantly, the effect of parasitic capacitance, etc.) degrade when increasing the size of the switch devices 12a-12n. Such degradation will add loss to the circuit 10, which effectively will reduce the Q factor that the large switching circuit is trying to improve.
Consider the formula Q=Xc/R, where Xc is the capacitive reactance and R is the resistance. Xc varies inversely with frequency. At higher frequencies, Xc becomes quite small for a given capacitor value. The value R is frequency invariant. Conventional approaches having significant fixed R can significantly limit potential Q values.
It would be desirable to implement a digitally variable capacitor that may have a high Q factor.